Nucleation and aggregation in atomic systems offer tremendous possibilities for making structures at the nanoscale that may be useful in a wide range of technologies, including nano and molecular electronics, high-density patterned media for data storage, optoelectronics, and nanosensor arrays. Examples of self assembly in atomic systems are ubiquitous in nature and technological applications and include precipitation of various phases in multi-component metallic alloys and island formation on crystalline semiconductor substrates. There has been much interest in utilizing the self-driving nature of nucleation and growth to produce nanostructures with precisely tailored size and/or spatial distributions.
The use of applied fields to pattern the nucleation and growth of microstructure within crystalline materials has been demonstrated. Technological interest in directed assembly within semiconductor hetero-systems stems in large part from the potential application of quantum dot arrays/superlattices in optoelectronics, spintronics, and quantum computing, and also in their potential integration with existing silicon complimentary metal-oxide semiconductor (CMOS) technology. A key requirement for such applications is accurate spatial positioning and size uniformity of clusters over a large area. Spatial control is required for addressability of each cluster, and in some applications (e.g. logic circuits), for building complex arrangements of dots into devices. Size uniformity is important because the quantum properties of a given nanocluster are sensitively dependent on the cluster size, strain state, and composition.
One highly promising example of a material system in which precise control of nanostructure formation would be highly desirable is the silicon/germanium (Si/Ge) heteroepitaxial system. Recent experimental effort has been directed towards development of approaches for spatial patterning of surface dots in the Si/Ge heteroepitaxial system. The most common approach has been to pre-pattern the substrate, either using traditional “top-down” approaches or by taking advantage of naturally self-assembled features. Examples of the latter include creating vicinal Si (100) surfaces to align dots at surface steps, employing the strain-field created by a planar misfit dislocation network at a relaxed Si/Si1-xGex interface, and using undulations created by the Asaro-Tiller-Grinfeld instability to direct Ge dot formation. While attractive, owing to the limited substrate pre-processing required, these approaches are generally not able to produce device-quality ordering of Ge dots.
On the other hand, substrate pre-patterning by various lithographic methods has led to promising demonstrations of dot patterning in the Si/Ge heterosystem. Electron-beam lithography and reactive ion etching (RIE) have been used successfully to generate periodic structures on Si surfaces which act to direct Ge dot formation. For example, SiGe island superlattices formed on etched trench arrays are able to transmit strain through multilayered heterostructures to produce ordered Ge dot arrays on a planar surface. Surface features including mesas and pits have been shown to provide strong driving forces for dot isolation, however, the influence of these complex geometries on the nucleation and growth of dots is not fully understood. Similar patterning has been observed using focused gallium ion beams to create locally preferential regions for subsequent formation of Ge islands. The primary drawbacks of these pre-patterning approaches are scalability of high-resolution lithography to large surface areas, and the additional steps required for planarizing the surface on which the dots are formed.
The growth of highly-ordered two-dimensional arrays of semiconductor quantum dots lends itself to a variety of technologically important applications, ranging from sensors, to data storage, to quantum computing. Finding a viable, cost-effective path for manufacturing ultra-high density arrays of uniform semiconductor quantum dots (with quantum confinement properties) on semiconductor substrates would be desirable.